Fast Power- and Slew-Aware Gated Clock Tree Synthesis
نویسندگان
چکیده
منابع مشابه
Power Aware Synthesis of Power Gated FSM
Power gating is often used to reduce power of a system which is in the form of a finite state machine (FSM). Power gating can be applied to turn OFF the inactive sub-machine which is obtained after partitioning the FSM by gating the supply voltage. Adjustment of supply voltage of one submachine for ON to OFF or OFF to ON state needs time, called wakeup time which affects the partitioning of FSM...
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Reducing Power dissipation is one of the crucial problems in today’s scenario. So this dissipation has become a bottleneck in the design of high speed synchronous systems which are operating at high frequency. Clock signals have been a great source of Power. Design can be made on the basis of Clock gating approach to reduce the consumption of clock’s signal switching power which is the foremost...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2012
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2011.2168834